This application claims priority to JP 2014-035050 filed Feb. 26, 2014 and JP2015-033787 filed Feb. 24, 2015, the entire disclosure of which is incorporated herein by reference.
1. Technical Field
The present invention generally relates to a semiconductor integrated circuit device (IC), and more particularly to a semiconductor integrated circuit device internally provided with an output buffer circuit having a tolerant function. Furthermore, the invention relates to an electronic appliance or the like that uses such a semiconductor integrated circuit device.
2. Related Art
The tolerant function is a function that prevents current from flowing from a signal terminal to a power supply even if a voltage higher than the power supply voltage is applied to the signal terminal from the outside. For example, in a semiconductor integrated circuit device, if a signal having a voltage higher than the power supply voltage is input to an input/output terminal connected to an input circuit and an output buffer circuit, in the output buffer circuit in which the signal is applied to a drain of a P channel MOS field effect transistor, it is necessary to prevent current from flowing from the drain into the power supply via a back gate of the P channel MOS field effect transistor.
Also, in the semiconductor integrated circuit device, in order to prevent destruction of an internal circuit caused by electrostatic discharge (ESD), generally, a protective diode is connected in a direction opposite to the voltage direction between the signal terminal and a power supply terminal. However, in the output buffer circuit having a tolerant function, it is not possible to connect a protective diode between a high potential-side power supply terminal and the signal terminal to which a potential higher than the high potential-side power supply potential is applied.
Accordingly, an ordinary output buffer circuit having a tolerant function is configured such that, when positive charges are applied to the signal terminal due to electrostatic discharge, a protective diode connected between the signal terminal and a low potential-side power supply terminal breaks down to cause a flow of reverse current, as a result of which the positive charges are discharged to the low potential-side power supply terminal. This configuration requires, as the protective diode, a large diode that can withstand heat generation caused by a surge current generated at the time of breakdown, which causes an increase in the area of the semiconductor substrate and an increase in the cost of the semiconductor integrated circuit device.
As a related technique, Japanese Patent No. 5082841 (paragraphs 0014-0015, FIG. 1) discloses a semiconductor device including an electrostatic discharge (ESD) protection circuit that does not require special tuning, can reduce processing steps and the development period, and can achieve a size reduction. The semiconductor device includes an input/output pad 101, a power supply voltage node VDE to which a power supply voltage is supplied, a reference potential node GND to which a reference potential is supplied, a first diode 131 whose anode is connected to the input/output pad 101 and whose cathode is connected to a first node BP, a potential control circuit 103 that is connected to the input/output pad 101 and the power supply voltage node VDE and is configured to, when a voltage lower than the power supply voltage is input into the input/output pad 101, perform control such that the first node BP has a voltage equal to the power supply voltage, a trigger circuit 109 that outputs a static electricity-on signal upon input of static electricity into the input/output pad 101, and an electrostatic discharge surge pass circuit 108 that, upon output of the static electricity-on signal, causes an electrostatic discharge current to flow between the first node BP and the reference potential node GND.
In the semiconductor device disclosed in Japanese Patent No. 5082841, a back gate of a P channel MOS field effect transistor 121 of an output buffer 110 is connected to the first node BP of an ESD protection circuit 106, and not to the power supply voltage node VDE. Accordingly, even when a voltage higher than the power supply voltage is applied to the input/output pad 101, current does not flow from the input/output pad 101 to the power supply voltage node VDE, and voltage is applied from the input/output pad 101 to the back gate of the transistor 121 via the first diode 131 or a P channel MOS field effect transistor 112. However, in the case where a plurality of input/output pads are provided in the semiconductor device, in order to separate the potentials of the back gates of the P channel MOS field effect transistors connected to the input/output pads, it is necessary to provide an ESD protection circuit for each input/output pad.
JP-A-H10-214940 (paragraphs 0011-0012, FIG. 1) discloses a semiconductor device designed to increase electrostatic destruction tolerance between a power supply terminal and a ground terminal without increasing the chip area or increasing the complexity of the layout design of an internal circuit. The semiconductor device includes a plurality of metal terminals provided on a semiconductor substrate, a first common discharge line connected commonly to each of at least some of the plurality of metal terminals, a second common discharge line connected commonly to each of at least some of the metal terminals, first electrostatic protection elements that are provided so as to correspond to at least some of power supply terminals and ground terminals out of the plurality of metal terminals and connects each of the power supply terminal and the ground terminal to the first common discharge line so as to protect the internal circuit from electrostatic destruction, and second electrostatic protection elements that are provided so as to correspond to at least some of power supply terminals and ground terminals out of the metal terminals and connects each of the power supply terminal and the ground terminal to the second common discharge line so as to protect the internal circuit from electrostatic destruction.
Furthermore, JP-A-2010-80472 (paragraphs 0017-0018, FIG. 1) discloses a semiconductor device including a plurality of circuit blocks having separated power supply systems, wherein the resistance against static electricity is improved. The semiconductor device includes a plurality of circuit blocks having separated power supply systems, a first group of diodes having anodes connected respectively to ground potential lines of the plurality of circuit blocks, a second group of diodes having cathodes connected respectively to the ground potential lines of the plurality of circuit blocks, and a floating common discharge line connected to the cathodes of the first group of diodes and the anodes of the second group of diodes.
JP-A-H10-214940 and JP-A-2010-80472 disclose one or more common discharge lines, but do not propose protective measures against electrostatic discharge for a signal terminal in a semiconductor integrated circuit device internally provided with an output buffer circuit having a tolerant function.
In a semiconductor integrated circuit device internally provided with an output buffer circuit having a tolerant function, it is not possible to connect a protective diode between a signal terminal and a high potential-side power supply terminal, and it is therefore necessary to take special protective measures against electrostatic discharge for the signal terminal. Accordingly, in view of the above, a first object of the invention is to, in a semiconductor integrated circuit device internally provided with an output buffer circuit having a tolerant function, eliminate the need for a large protection diode that can withstand heat generation caused by a surge current generated at the time of breakdown, and suppress the increase in the area of the semiconductor substrate and the increase in the cost of the semiconductor integrated circuit device by causing only a forward current to flow through a protective diode. A second object of the invention is to, even when a plurality of output buffer circuits connected respectively to a plurality of signal terminals are provided, protect the internal circuit from electrostatic discharge without causing interference between the plurality of output buffer circuits, with a simple circuit configuration.